The present invention relates to the structure of an LD (Lateral Double Diffused) MOS transistor as a high breakdown voltage element.
Patent Document 1 (Japanese Unexamined Patent Publication No. 2000-22142, FIG. 1) discloses the structure of a P-channel LDMOS transistor. In this structure, for an N-type semiconductor substrate, an N-channel well region and a drain region are formed in a P-type well region formed over the semiconductor substrate; a source region is formed in the N-channel well and a gate electrode is formed through an insulating film over the N-channel well region. For a P-type semiconductor substrate, a P-type well region is formed in an N-type well region formed over the semiconductor substrate and a drain region is formed there; a source region is formed in the N-type well region and a gate electrode is formed through an insulating film over the N-type well region.
Patent Document 2 (Japanese Unexamined Patent Publication No. 2001-308321, FIG. 7) and Patent Document 3 (Japanese Unexamined Patent Publication No. 2002-176173, FIG. 8) disclose the structure of an N-channel LDMOS transistor. In this structure, a P-type low-concentration impurity region and an N-type low-concentration impurity region are formed in an N-type well region formed over a P-type semiconductor substrate; a drain region is formed in the N-type low-concentration impurity region; a source region is formed in the P-type low-concentration impurity region; and a gate electrode is formed over the P-type impurity region through an insulating film.